About Us

Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just four years, we have raised a total of $120 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

Position Overview

We are seeking a Silicon Logical Design Principal Engineer to drive technical leadership across our digital design organisation. In this role, you will own and deliver organisation wide, multi year technical goals for AI accelerator SoCs from specification through tape out. You will combine deep technical expertise with technical influence across multiple teams and programs to drive execution, quality, and innovation.

This is a hands on technical role for someone who thrives at the intersection of architecture, implementation, and cross functional influence in a fast paced startup environment. You will operate without direct management responsibility, instead leading through technical excellence, mentorship, and strategic vision.

Key responsibilities:

Technical Leadership
- Own organisation-wide, multi-year technical direction across teams and silicon programs
- Define system-level architectures for AI accelerator SoCs aligned to long-term strategy
- Make high-impact technical decisions under ambiguity and align the organisation behind them
Execution and Delivery
- Drive system and micro-architecture specs through high-quality RTL implementation
- Deliver large, high-risk programs under tight schedules
- Lead validation, bring-up, debug, and silicon issue root-cause analysis
Cross-Functional Collaboration
- Partner across architecture, verification, physical design, software, product, and DFT
- Translate technical capability into product roadmaps and customer value
- Identify and execute company-wide opportunities across organisational boundaries
Engineering Excellence
- Set and enforce standards for RTL quality, reuse, and design reviews
- Establish the bar for engineering processes, quality, and execution
- Introduce mechanisms to measure and communicate customer impact
Mentorship and Knowledge Sharing
- Mentor senior engineers and provide direct, constructive feedback
- Scale knowledge through documentation, talks, and technical guidance
- Hire and attract senior talent in partnership with leadership
Leadership Expectations
- Drive business outcomes through influence and cross-functional leadership
- Optimise for the broader organisation, not local teams
- Communicate clearly, lead difficult decisions, and encourage bold, accountable execution
- Uphold and shape Axelera’s culture and values

Qualifications:

Extensive experience in digital and logical design for complex SoCs with multiple successful tape outs

Strong expertise in RTL and micro architecture development (SystemVerilog and Verilog)

Experience with large scale SoC integration including CPUs, accelerators, memory subsystems, and interconnects

Solid understanding of performance, power, and area trade offs in advanced process nodes

Experience working closely with verification and physical design teams to achieve functional and timing closure

Track record of delivering organisation wide, multi year technical initiatives

Demonstrated ability to influence technical direction without direct management authority

Strong communication skills and the ability to operate at both strategic and hands on technical levels

+ Preferred:

Experience with AI and ML accelerators, GPUs, NPUs, or high performance compute architectures

Familiarity with industry standard interconnects such as AXI and NoC architectures

Knowledge of low power design techniques and multi clock or multi voltage systems

Experience with silicon bring up, post silicon debug, and root cause analysis

Experience working in a startup or fast scaling environment

History of contributing to industry standards, patents, or technical publications

Location

We offer a flexible working arrangement, with options to:

Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity.
Work fully remotely from any European country (incl. the UK) you are already in.
Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).

What we offer 

This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. 

An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. 

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.

Principal Engineer - Silicon Logical Design

Benefits

Job Description