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Job Description:

Drive architecture and design of high-speed SoC subsystems and interfaces from concept through integration. Define micro-architecture, write clear specifications, and collaborate with RTL, verification, firmware, and physical design teams. Develop and review RTL/design implementations for performance, power, area, and testability trade-offs. Lead block- and system-level bring-up, debug, and root-cause analysis across simulation, emulation, and silicon. Own documentation, design reviews, and cross-functional execution to deliver robust, production-ready SoC features. Experience in developing complex bare-metal firmware mainly in C (but also assembly) on ARM Cortex-M and RISC-V processors Good understanding of embedded firmware/software development process Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, Watchdog, Timer, UART, Ethernet, PCIe and USB Design knowledge with RTL coding in Verilog / VHDL Experience in using FPGA tool flow. Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Strong commitment to quality and customer satisfaction Excellent verbal and written communication skills in English Mentor junior validation engineers Able to travel 0-2 times annually if required. Must be willing to work outside of normal business hours to match timing with India Standard Time as well as Pacific Standard time Must be adept with using AI tools to automate design builds and processes

Requirements/Qualifications:

Minimum qualifications

: BS EE /CE with 7+yrs OR MS EE/CE with 6+ years, and experience in SoC architecture, embedded software design and debug
: In-depth knowledge of FPGA/SoC architectures, hardware architectures, system-level IC design, and end-use scenario creation
Validation & Debug: Strong background in SoC prototype emulation, silicon validation, failure analysis, and debug
Lab Skills: Board-level debug on PCBs (digital logic & analog circuits) using oscilloscopes, logic analyzers, protocol analyzers/exercisers, integrated logic analyzers (Synopsys Identify, Xilinx ChipScope, Altera SignalTap or Lattice Reveal)
Debug Tools: CPU debug (SoftConsole, EWARM, Keil); Trace debug (Lauterbach, Ultradevelop)
: C/C++, assembly; bare-metal firmware on ARM Cortex-M and RISC-V; diagnostic code (bare-metal, Zephyr, RTOS, embedded Linux)
Standards & Peripherals: JTAG, SVF, IEEE 1532, STAPL; validation of SPI, I2C, UART, Ethernet, PCIe, USB
RTL & EDA: Verilog/VHDL coding; Simulation (ModelSim), Synthesis (Synplicity)
Soft Skills: Strong communication (English), quality commitment

Preferred qualifications

Coding standards & static analysis; Atlassian (Confluence, JIRA), Bitbucket, Git; Perl/TCL scripting;
Emerging Tech: Agentic AI for embedded software development and peripheral driver debug (e.g. such as Claude Code, ChipAgents, Github Co-pilot etc.)
High-Speed SERDES: Bring-up and debug of 32Gbps PCS/PMA controllers
Serial Protocols (PHY through transaction layers):
- Aurora, Ethernet (1G–400G, SGMII/XGMII variants), USB 3.0
- SERDES Controllers: PCIe Gen3/4/5, Interlaken, OTN/SONET/SDH, xPON, JESD204C
- SDI (SD/HD/3G/12G), DisplayPort, HDMI
- CPRI, Serial RapidIO, SATA, Fiber Channel, CoaXpress, HMC, Firewire

Percentage of time spent:

Documentation – 20% Design Creation & Verification – 30% Lab Bringup & Debug – 50%

Essential Physical Functions and Working Conditions:

50 % work in front of computer 50% work in the lab

Travel Time:

0% - 25%

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

SoC Validation Engineer (Senior Engineer II)

Job Description