Job Details:

Job Description:

In this position, you will become a member of the digital design team delivering next-generation NPUs for AI PCs. As part of this high-performance team, you will be involved in the digital design of super efficient, low power IP to run the latest AI models. The team is looking to hire an engineer with an interest in RTL development and in artificial intelligence.

Your responsibilities will include:

Developing the micro-architectural specification of complex design block(s).
Logic implementation of complex design block(s) using RTL coding techniques.
Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.
Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.
Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.

Qualifications:

Required Experience:

Exposure to RTL level Digital Design using System Verilog and/or Verilog.
Proven track record of successful delivery of projects.
A self-starter with the ability to manage your own time effectively and clearly communicate your ideas.
Ability to work well in a diverse team environment.

Preferred:

Experience in ASIC, SoC, or FPGA design experience.
Experience with industry-standard development tools and methodologies.
Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.
Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).
Understanding topics such as model quantization, emerging data types etc., and their usage in inference for CNNs, LLMs and other deep learning models.

Job Type:

Experienced Hire

Shift:

Shift 1 (Ireland)

Primary Location:

Ireland, Leixlip

Additional Locations:

Business group:

The Software and AI (SAI) Team drives customer value by enabling differentiated experiences through leadership AI technologies and foundational software stacks, products, and services. The group is responsible for developing the holistic strategy for client and data center software in collaboration with OSVs, ISVs, developers, partners and OEMs. The group delivers specialized NPU IP to enable the AI PC and GPU IP to support all of Intel's market segments. The group also has HW and SW engineering experts responsible for delivering IP, SOCs, runtimes, and platforms to support the CPU and GPU/accelerator roadmap, inclusive of integrated and discrete graphics.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Deep Learning Hardware Design Engineer

Job Description